Modern electric memory devices such as flash memory devices erase data bits in parallel. As a result, to update a block of memory, the memory device portion in which the update data is to be stored is first erased and then the entire block is then written (with the updated bits or bytes) to the erased memory device portion. In addition, to improve the yield and lower the cost of large capacity memory devices, error detecting and error correcting bits are appended to the block. This approach requires that the unchanging data from the prior block is known.
New cross point memory arrays are being utilized to store data in applications that were previously served by flash memory devices. As with flash memory devices, error detecting and error correcting techniques are being used to improve yield. Because, since cross point memory arrays can be erased on a byte-wise or even a bit-wise basis (as opposed to the bulk erase requirements of flash memory devices), and because each time a memory cell is written its ability to be written again degrades (a property called endurance), it is desirable to only change those bits or bytes that have changed. New cross point memory arrays that use phase-change information storage elements such as those found in PCM or PRAM devices (or, in some cases, resistive change information storage elements such as those found in RRAM devices) that wear out much more slowly than charge storage information storage elements (such as floating gate devices such as those found in flash memory devices) will particularly benefit from the present invention due to the reduced load balancing that enables the same physical storage locations to be written and rewritten without relocating the sector to a different area of the memory device.
What is needed is an error correcting technique that can be made more efficient by adjusting the error correcting bits from a previous computation of the error detecting and correcting bits for a storage block rather than regenerating the error detecting and correcting bits for the entire block. What is needed is a cross point memory array that works with an incrementally modifiable ECC. The present invention fills this need by reversing the error correcting code (ECC) and backing out prior values and replacing them with new values without recomputing the entire ECC.